Title :
Self-timed boundary-scan cells for multi-chip module test
Author :
Garcia, T.A. ; Acosta, Antonio J. ; Mora, J.M. ; Ramos, J. ; Huertas, Jose Luis
Author_Institution :
Inst. de Microelectron. de Sevilla, CNM
Abstract :
This communication presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing in a Smart-Substrate MCM. Three different self-timed asynchronous scan cells are proposed (Sense, Drive and Drive and Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode
Keywords :
VLSI; asynchronous circuits; boundary scan testing; integrated circuit interconnections; logic testing; multichip modules; Smart-Substrate MCM; digital testing; drive cells; multi-chip module test; scan-path architecture; self-timed boundary-scan cells; sense cells; synchronous environment; Automatic testing; Circuit faults; Circuit testing; Clocks; Costs; Driver circuits; Flip-flops; Integrated circuit testing; Protocols; Synchronization;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670854
