Analysis of the New Latchup Model for Deep Sub-micron Integrated Circuits

Author

Dong, Pan ; Fan, Long ; Yue, Suge ; Zheng, Hongchao ; Du, Shougang

Author_Institution

Design Dept., Beijing Microelectron. Technol. Inst., Beijing, China

fYear

2011

fDate

12-14 Dec. 2011

Firstpage

56

Lastpage

62

Abstract

The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current. The origin model was improved based on the simulated results. The result studying the improved latch up model shows that the smaller ratios of the internal parasitic resistors between R_W1 and R_W2 or R_S1 and R_S2 could lead to smaller latch up current and delay more time for the latch up occurrence.

Keywords

CMOS integrated circuits; integrated circuit modelling; CMOS inverter; NMOS; PMOS; PNP transistor; SEL happening process; deep sub-micron integrated circuits; intrinsic parasitic lateral NPN; latchup model; size 0.18 mum; CMOS integrated circuits; Cathodes; Integrated circuit modeling; Logic gates; MOS devices; Transient analysis; Transistors; (SEL); Single event effects (SEE); inverter; large scale integrated circuit (VLSI); model; transistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Dependable, Autonomic and Secure Computing (DASC), 2011 IEEE Ninth International Conference on

Conference_Location

Sydney, NSW

Print_ISBN

978-1-4673-0006-3

Type

conf

DOI

10.1109/DASC.2011.34

Filename

6118353