Title :
Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
This brief considers circuits with multiple scan chains where each scan chain can operate in shift, functional, or hold mode independently of the other scan chains. For circuits where the hardware overhead of controlling the scan chains independently is acceptable, this brief describes a procedure whose goal is to generate a test set that achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests, but where the shift mode is used as few times as possible during the first patterns of the tests. This allows the circuit to operate closer to its functional operation conditions, and reduces the power dissipation during the second patterns of the tests, which are applied at-speed.
Keywords :
boundary scan testing; design for testability; functional operation conditions; hardware overhead; independent scan chain modes; power dissipation; reduced power transition fault test sets; shift mode; skewed-load tests; transition fault coverage; Circuit faults; Clocks; Delay; Power dissipation; Switches; Vectors; Very large scale integration; Design-for-testability; full-scan circuits; switching activity; transition faults; two-pattern tests;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2012.2207137