DocumentCode
2859458
Title
The razorback CCD: A high-performance parallel input delay line architecture
Author
Shott, J. ; Melen, R.
Author_Institution
Stanford Electronics Lab., Stanford, CA, USA
Volume
XVIII
fYear
1975
fDate
27426
Firstpage
150
Lastpage
151
Abstract
An analog CCD delay line with multiple input taps which can be used singly to provide a selectable bit delay, or in parallel to perform delay-sum and multiplexing signal operations, will be covered. These taps are realized along the delay line with high transfer efficiency and large bandwidth.
Keywords
Bandwidth; Charge coupled devices; Charge transfer; Clocks; Delay effects; Delay lines; Frequency conversion; Frequency measurement; Propagation delay; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International
Type
conf
DOI
10.1109/ISSCC.1975.1155445
Filename
1155445
Link To Document