A new systolic architecture for 2-D FIR digital filters

Two dimensional FIR digital filters are important in two dimensional image and signal processing. Systolic architectures have the benefit of gaining most from VLSI in time cost effective terms and much work has been done in creating reconfigurable array structures so as to produce flexible but specialised systems for tasks such as: image enhancement; image restoration; and image coding. The authors describe a novel variant architecture devised while considering the above. The proposed architecture arranges the input coefficient stream and the input data stream in a manner which removes the need to clear processing element latches before the beginning of every row scan. The `speed up´ obtained is enhanced by fully pipelining each pathway. The improved features in the design provide high throughput appropriate to real time applications and was, derived directly from the filter transfer function