Title :
Hierarchical statistical inference model for specification based testing of analog circuits
Author :
Yoon, Heebyung ; Variyam, Pramodchandran ; Chatterjee, Abhijit ; Nagi, Naveena
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process
Keywords :
VLSI; analogue integrated circuits; circuit analysis computing; inference mechanisms; integrated circuit testing; piecewise-linear techniques; sensitivity analysis; statistical analysis; analog ICs; circuit parameter variations; critical circuit specifications; design hierarchy; hierarchical statistical inference model; high level system specifications; linear sensitivity functions; piecewise linear sensitivity functions; specification based testing; statistical distributions; Analog circuits; Circuit testing; Computational modeling; Distributed computing; Logic testing; Manufacturing processes; Monte Carlo methods; Piecewise linear techniques; Statistical distributions; System testing;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670862
