On removing redundant faults in synchronous sequential circuits

Author

Lin, Xijiang ; Pomeranz, Irith ; Reddy, Sudhakar M.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1998

fDate

26-30 Apr 1998

Firstpage

168

Lastpage

175

Abstract

We describe a time-efficient procedure for removing sequentially redundant faults from synchronous sequential circuits with synchronizing sequences. We use the properties of redundant faults and propose several methods to identify subsets of redundant faults that can be removed simultaneously from the circuit. By removing several redundant faults simultaneously, the number of repetitions of the test generation procedure invoked to identify redundant faults is reduced. Experimental results presented in this work demonstrate the effectiveness of the proposed removal procedure

Keywords

automatic testing; integrated circuit testing; integrated logic circuits; logic testing; redundancy; sequences; sequential circuits; redundant fault identification; redundant faults removal; synchronizing sequences; synchronous sequential circuits; test generation procedure; time-efficient procedure; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Electrical fault detection; Fault detection; Fault diagnosis; Logic circuits; Redundancy; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670865

Filename

670865