Title :
Stress testing FET gates without the use of test patterns
Author_Institution :
IBM System Development Division, Manassas, VA, USA
Abstract :
This paper will cover a technique for stressing of all FET gates in LSI dynamic random logic FET circuits. This is accomplished by reversing the sequence of the clock signals. No input test patterns are required.
Keywords :
Circuit testing; Clocks; Combinational circuits; FETs; Logic circuits; Logic devices; Logic gates; Logic testing; Stress; System testing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International
DOI :
10.1109/ISSCC.1975.1155458
