Impedance mismatch and lumped capacitance effects in high frequency testing

Working at high frequency adds to VLSI designers and test engineers many constraints. Many effects which are insignificant at low frequency domain have to be taken into account. These effects alternate considerably the precision of the test, introducing the a new challenge to the test community. The impedance mismatch between the circuit under test output impedance and the characteristic impedance of the transmission line as well as the effect of the lumped capacitance at the input of the tester comparator are among the most important effects. These two effects result as ringings, overshoot and timing delay. In this paper we present a method to eliminate the aberrations of the transmission line effects as well as the influence of the lumped capacitance at the input of the DUT thereby improving the precision of the rest