Title :
A study on the utility of using expected quality level as a design for testability metric
Author :
Williams, Douglas ; Ferguson, F. Joel ; Larrabee, Tracy
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
This paper develops a Physical Design for Test (PDFT) metric that is directly related to the expected quality level (QL) contribution of a cell to a circuit, and it details experimental results showing the usefulness of this metric in predicting the quality level contribution of a cell to circuits that have yet to be designed. The PDFT metric shows what QL increase can be expected for the circuit by changing the physical design of a component of the circuit
Keywords :
automatic testing; circuit layout CAD; design for testability; integrated circuit testing; logic CAD; logic testing; PDFT metric; Physical Design for Test; physical design; quality level; testability; testability metric; Circuit faults; Circuit testing; Design for testability; Electrical fault detection; Fault detection; Integrated circuit testing; Logic arrays; Logic circuits; Logic testing; Semiconductor device testing;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670880
