Title :
Partial reset and scan for flip-flops based on states requirement for test generation
Author :
Liang, Hsing-Chung ; Lee, Chung Len ; Chen, Jwu E.
Author_Institution :
Dept. of Electr. Eng., Van Nung Inst. of Technol., Chung-Li, Taiwan
Abstract :
This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits
Keywords :
design for testability; fault diagnosis; flip-flops; logic testing; sequential circuits; fault activation; fault propagation; flip-flops; hard-to-detect faults; partial reset; partial scan; sequential circuits; states requirement; test generation; undetectable faults; untestable faults; Circuit faults; Circuit testing; Delay effects; Design for testability; Electronic equipment testing; Flip-flops; Hardware; Routing; Sequential analysis; Sequential circuits;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670888