A structural approach for space compaction for concurrent checking and BIST

Author

Seuring, M. ; Gössel, M. ; Sogomonyan, E.

Author_Institution

Inst. of Comput. Sci., Potsdam Univ., Germany

fYear

1998

fDate

26-30 Apr 1998

Firstpage

354

Lastpage

361

Abstract

In this paper a new structural method for linear output space compaction is presented. The method is applicable to concurrent checking and built-in self test (BIST). Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs output partitions are determined without fault simulation. For all ISCAS 85 benchmark circuits three groups of compacted outputs are sufficient to achieve 100% fault coverage in test mode and for 3 to 5 groups an error detection probability of 98% is obtained in on-line mode. The method can be applied to very large circuits

Keywords

VLSI; built-in self test; error detection; integrated circuit testing; logic partitioning; logic testing; BIST; ISCAS 85 benchmark circuits; benchmark circuits; built-in self test; concurrent checking; linear output space compaction; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computer science; Electrical fault detection; Fault detection;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670890

Filename

670890