• DocumentCode
    2860042
  • Title

    A Distributed Task Migration Scheme for Mesh-Based Chip-Multiprocessors

  • Author

    Yaghoubi, Hossein ; Modarresi, Mehdi ; Sarbazi-Azad, Hmid

  • Author_Institution
    Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
  • fYear
    2011
  • fDate
    20-22 Oct. 2011
  • Firstpage
    24
  • Lastpage
    29
  • Abstract
    A task migration scheme for homogeneous chip multiprocessors (CMP) is presented in this paper. The proposed migration mechanism focuses on the communication sub-system and aims to reduce the total power consumption and latency of the network-on-chip (NoC). In this work, starting from an initial mapping, the tasks migrate to new cores in such a way that the distance between the end-point nodes of high-volume communication flows is reduced. Finding the new place for a task is done in a distributed manner by applying an iterative local search that relies on the local information of each task about its communication demand. The task migration procedure also includes a pre-migration step that aims to produce a high quality (i.e. closer to the optimum point) starting point for the main distributed algorithm. The experimental results under some synthetic and realistic CMP workloads show that this method can effectively adapt the mapping of the tasks to the on-chip communication pattern and improve the power consumption and performance of the on-chip networks.
  • Keywords
    distributed algorithms; iterative methods; multiprocessing systems; network-on-chip; power aware computing; power consumption; task analysis; communication subsystem; distributed algorithm; distributed task migration scheme; end-point node; high volume communication; homogeneous chip multiprocessor; initial mapping; iterative local search; mesh-based chip-multiprocessor; migration mechanism; network-on-chip; on-chip communication pattern; on-chip network performance; power consumption; realistic CMP workload; synthetic CMP workload; task migration procedure; Algorithm design and analysis; Benchmark testing; Heuristic algorithms; Partitioning algorithms; Power demand; Program processors; System-on-a-chip; Graph partitioning; NoC; Power consumption; Task migration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Computing, Applications and Technologies (PDCAT), 2011 12th International Conference on
  • Conference_Location
    Gwangju
  • Print_ISBN
    978-1-4577-1807-6
  • Type

    conf

  • DOI
    10.1109/PDCAT.2011.2
  • Filename
    6118527