• DocumentCode
    2860148
  • Title

    Fault models and tests for two-port memories

  • Author

    van de Goor, A.J. ; Hamdioui, S.

  • Author_Institution
    Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
  • fYear
    1998
  • fDate
    26-30 Apr 1998
  • Firstpage
    401
  • Lastpage
    410
  • Abstract
    In this paper the effects of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n 2), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account
  • Keywords
    SRAM chips; computational complexity; fault diagnosis; integrated circuit testing; integrated memory circuits; two-port networks; SRAM; complexity; fault models; functional faults; march tests; memory topology; two-port memories; Computer architecture; Decoding; Electronic mail; Fault detection; Information technology; Logic arrays; Multiprocessing systems; System testing; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1998. Proceedings. 16th IEEE
  • Conference_Location
    Monterey, CA
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-8436-4
  • Type

    conf

  • DOI
    10.1109/VTEST.1998.670898
  • Filename
    670898
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2860148