Title :
An approach to modeling and testing memories and its application to CAMs
Author :
Sidorowicz, Piotr R. ; Brzozowski, Janusz A.
Author_Institution :
Dept. of Comput. Sci., Waterloo Univ., Ont., Canada
Abstract :
An approach to modeling and testing memories is presented and illustrated using an n-word by l-bit (n×l) static content-addressable memory (GAM) array for cell input stuck-at faults. An input stuck at fault model for a CAM is defined, and a test of length 7n+2l+5 with 100% fault coverage with respect to this fault model is constructed. This test also detects all the usual cell stuck-at and transition faults. Finally, some design-for-testability (DFT) modifications facilitating a further reduction of this test´s length are proposed
Keywords :
CMOS memory circuits; content-addressable storage; design for testability; fault diagnosis; finite state machines; integrated circuit testing; logic testing; semiconductor device models; CAM; design-for-testability modifications; fault coverage; fault model; modeling; n-word; static content-addressable memory array; stuck-at faults; testing; Application software; CADCAM; Cams; Circuit faults; Circuit testing; Computer aided manufacturing; Computer science; Fault detection; Random access memory; System testing;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670899
