An approach to modeling and testing memories and its application to CAMs

Author

Sidorowicz, Piotr R. ; Brzozowski, Janusz A.

Author_Institution

Dept. of Comput. Sci., Waterloo Univ., Ont., Canada

fYear

1998

fDate

26-30 Apr 1998

Firstpage

411

Lastpage

416

Abstract

An approach to modeling and testing memories is presented and illustrated using an n-word by l-bit (n×l) static content-addressable memory (GAM) array for cell input stuck-at faults. An input stuck at fault model for a CAM is defined, and a test of length 7n+2l+5 with 100% fault coverage with respect to this fault model is constructed. This test also detects all the usual cell stuck-at and transition faults. Finally, some design-for-testability (DFT) modifications facilitating a further reduction of this test´s length are proposed

Keywords

CMOS memory circuits; content-addressable storage; design for testability; fault diagnosis; finite state machines; integrated circuit testing; logic testing; semiconductor device models; CAM; design-for-testability modifications; fault coverage; fault model; modeling; n-word; static content-addressable memory array; stuck-at faults; testing; Application software; CADCAM; Cams; Circuit faults; Circuit testing; Computer aided manufacturing; Computer science; Fault detection; Random access memory; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670899

Filename

670899