Characterization and failure analysis of Sub-10 nm diameter, gate-all-around nanowire field-effect transistors subject to electrostatic discharge (ESD)

Author

Liu, W. ; Liou, J.J. ; Singh, N. ; Lo, G.Q. ; Chung, J. ; Jeong, Y.H.

Author_Institution

Sch. of EECS, Univ. of Central Florida, Orlando, FL, USA

fYear

2011

fDate

21-24 June 2011

Firstpage

1

Lastpage

2

Abstract

Electrostatic discharge (ESD) robustness of the Sub-10 nm diameter gate-all-around nanowire field-effect transistor (NW FET) was characterized and compared with sub 65nm MOS devices and FinFETs. Failure mechanisms of NW FETs subject to ESD stresses are investigated by DC current-voltage measurements carried out before and after stressing the devices with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester.

Keywords

MIS devices; MOSFET; electrostatic discharge; failure analysis; nanowires; DC current-voltage measurements; ESD; FinFET; MOS device; NW FET; TLP tester; electrostatic discharge; failure analysis; gate-all-around nanowire field-effect transistors; size 10 nm; size 65 nm; transmission line pulsing tester; Electrostatic discharge; Failure analysis; FinFETs; Layout; Logic gates; Stress; Nanowire field-effect transistor; electrostatic discharge (ESD); failure analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoelectronics Conference (INEC), 2011 IEEE 4th International

Conference_Location

Tao-Yuan

ISSN

2159-3523

Print_ISBN

978-1-4577-0379-9

Electronic_ISBN

2159-3523

Type

conf

DOI

10.1109/INEC.2011.5991616

Filename

5991616