Title :
Associative logic for logic network implementation
Author_Institution :
General Electric Co., Syracuse, NY, USA
Abstract :
This paper will cover a development, using bipolar design, capable of implementing combinational or sequential, multi-level, multiple-output, LSI logic networks containing over 100 gates. Ten circuit blocks, each comprising a logic matrix and an amplifier section, are used. Approach is based on Si monolithic Schottky technology resulting in die area of approximately 24,000 square mils.
Keywords :
Costs; Input variables; Logic arrays; Logic circuits; Logic design; Logic devices; Logic testing; Programmable logic arrays; Read only memory; Space technology;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1976 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1976.1155511
