Accelerating Symmetric and Asymmetric Ciphers with Register File Extension for Multi-word and Long-word Operation

In this paper, we propose a new register file architecture called the register file extension for multi-word and long-word operation (RFEMLO) to accelerate both symmetric and asymmetric cryptographic algorithms. Based on the idea that most of cryptographic algorithms heavily use multi-word or long-word operations, RFEMLO allows multiple contiguous registers to be specified as a single operand. RFEMLO can be applied to a general purpose processor by providing an instruction set extension and an additional functional unit. To evaluate the performance of RFEMLO, we use Simplescalar/ARM 3.0 (with gcc 2.95.2) and run detailed simulations on various cryptographic algorithms. The simulation results show that we could achieve 83% and 138% performance gain in both symmetric and asymmetric ciphers by applying RFEMLO to a conventional superscalar processor.