Nano-scale Si-capping thicknesses impacting junction performance on <110> silicon substrate

Silicon capping layer is a useful dielectric smoothing the interface integrity between gate dielectric and SiGe deposition layer in nano-scale process technology and reducing the possibility of Ge atom diffusion into the gate dielectric. However, the junction performance in reverse saturation current is suffered. Through the deliberate pattern design, the fringe junction leakage for MOSFET device was effectively extracted. The thicker Si capping layer well prevents Ge atom from diffusing into gate dielectric, but causes more fringe junction leakage at source/drain sites.