DocumentCode
2860875
Title
A dynamic priority arbiter for Network-on-Chip
Author
Wang, Jian ; Li, Yubai ; Peng, Qicong ; Tan, Taiqiu
Author_Institution
Sch. of Commun. & Inf. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2009
fDate
8-10 July 2009
Firstpage
253
Lastpage
256
Abstract
For some customized network-on-chip, the communication requirements among IP cores are usually non-uniform, which make the loads of input ports in one router are not balance. In order to improve the performance of network-on-chip, we proposed a dynamic priority arbiter. The arbiter detect the loads of input ports in every clock cycle and adjust the priority of each input port dynamically, then authorize one input ports to transfer data based on lottery mechanism. Under the uniform traffic mode in network-on-chip and non-uniform traffic mode such as an application of MPEG4 decoder in network-on-chip, we compared the performance between network-on-chip based on round-robin arbiter and network-on-chip based on dynamic priority arbiter proposed in this paper. The result shows: under non-uniform traffic mode, the dynamic priority arbiter can improve the communication performance of network-on-chip and reduce the requirement of buffer resource in network interface.
Keywords
network-on-chip; IP cores; MPEG4 decoder; buffer resource; dynamic priority arbiter; lottery mechanism; network interface; network-on-chip; round-robin arbiter; Clocks; Decoding; Digital signal processing; Feedback; MPEG 4 Standard; Network interfaces; Network-on-a-chip; Processor scheduling; Round robin; Telecommunication traffic; Arbiter; Network-on-Chip; buffer resource; network performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Embedded Systems, 2009. SIES '09. IEEE International Symposium on
Conference_Location
Lausanne
Print_ISBN
978-1-4244-4109-9
Electronic_ISBN
978-1-4244-4110-5
Type
conf
DOI
10.1109/SIES.2009.5196222
Filename
5196222
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