Deterioration of junction performance with temperature effect for 45 nm Si-capping MOSFETs on <110> silicon substrate

Adopting silicon capping layer is a promising method reducing the defect of interface between gate dielectric and SiGe deposition layer in the technology of manufacturing nano-scale devices and avoiding Ge atom diffusion into the gate dielectric or increasing the channel surface roughness. However, the junction leakage at refilled SiGe source/drain technology becomes worse. Through the deliberate pattern design, the fringe junction leakage for MOSFET devices was effectively extracted. The thicker Si capping layer well prevents Ge atom from diffusing into gate dielectric, but causes more fringe junction leakage at source/drain sites.