Extending VHDL for mixed mode simulation

The ability of VHDL to describe circuits and systems at different levels of abstraction together with a well defined standard has allowed it to become a universally recognized HDL for describing digital circuits. The many powerful features of VHDL make it ideal for documenting circuits and the way in which the language is defined means that repeatable results, with very few exceptions, are guaranteed even if circuits are simulated on different platforms running simulators from different vendors. However as VHDL was primarily designed as an HDL for digital circuits it has several limitations when mixed mode systems containing analogue elements need to be described and simulated. This limitation is becoming more obvious as manufacturers strive to produce ASIC devices which contain more functionality because many of these system contain analogue parts. With VHDL it is possible to simulate mixed mode system at the behavioural level if suitable models can be derived but when circuit level simulation is required most engineers are forced to use SPICE or one of it´s derivatives. There are several VHDL programs available which offer some analogue simulation capabilities but these are very limited in their scope