The requirements for a VHDL based custom IC, ASIC or FPGA design process

Examines a VHDL based design process and outlined some requirements for the tools and processes used in such a design process. Whilst doing this the author identifies a number of key areas where integration between tools and processes is important: a mixture of VHDL and standard graphical notations (DFD) and (FSM) is needed to specify the design in a way that can easily be communicated between different disciplines involved in the system design and partitioning; a common VHDL analyser/compiler for the simulation and synthesis tools will eliminate the risk of different interpretations of VHDL for simulation and synthesis; a mixed level simulation environment is desired where VHDL and high accuracy high performance gate level blocks can be simulated together; and scan insertion should he performed by the synthesis/optimisation tool and this should be closely integrated with the ATPG tool