Analyses of the influences of layout and process modifications on thin-film transistors with metal-induced lateral crystallized poly-Si nanowire channels

In this paper, we investigate the effects of layout design and re-crystallization temperature on the performance of poly-Si thin-film transistors (TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the on-state behavior could be enhanced at a lower re-crystallization temperature because of reducing smaller solid-phase-crystallized (SPC) grains in the channel.