Low temperature polycrystalline Si nanowire devices with gate-all-around Al2O3/TiN structure using an implant-free technique

Author

Tsai, T.I. ; Chao, T.S. ; Su, C.J. ; Lin, H.C. ; Huang, T.Y. ; Wei, Y.J.

Author_Institution

Dept. of Electrophys., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2011

fDate

21-24 June 2011

Firstpage

1

Lastpage

2

Abstract

In this work, for the first time, we propose and demonstrate an implant-free gate-all-around (GAA) low-temperature poly-Si (LTPS) nanowire (NW) device with Al₂O₃ dielectric and TiN gate. Since the channel and source/drain (S/D) regions are sharing one in-situ phosphorous-doped poly-Si material, the process cost could be efficiently reduced. Such novel scheme appears to be promising for both system-on-panel (SOP) and three dimensional IC applications. High on-off current ratio and on-state performance are demonstrated for the new device.

Keywords

field effect transistors; nanowires; semiconductor quantum wires; three-dimensional integrated circuits; Al₂O₃-TiN; gate-all-around structure; high on-off current ratio; implant-free technique; low temperature polycrystalline nanowire devices; on-state performance; one in-situ phosphorous-doped poly-Si material; system-on-panel; three dimensional IC; Aluminum oxide; Logic gates; Nanoscale devices; Silicon; Substrates; Tin; Si nanowire (Si NW); gate-all-around (GAA); in-situ doped channel; low temperature poly-Si (LTPS);

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoelectronics Conference (INEC), 2011 IEEE 4th International

Conference_Location

Tao-Yuan

ISSN

2159-3523

Print_ISBN

978-1-4577-0379-9

Electronic_ISBN

2159-3523

Type

conf

DOI

10.1109/INEC.2011.5991733

Filename

5991733