• DocumentCode
    2862549
  • Title

    Vertically-stacked bottom- and top- gate polycrystalline silicon TFTs for three dimensional integrated circuit

  • Author

    Lee, I-Che ; Tsai, Tsung-Che ; Tsai, Chun-Chien ; Yang, Po-Yu ; Wang, Chao-Lung ; Cheng, Huang-Chung

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2011
  • fDate
    21-24 June 2011
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A high-performance poly-Si TFT with bottom-gate structure and a top-gate poly-Si TFT were vertically stacked for three dimensional integrated circuit. Consequently, the n-channel poly-Si TFTs with bottom-gate structure on the bottom layer showed considerably improved electrical characteristics, such as a high field effect mobility of 390 cm2/V-s due to the large lateral grain formed in the channel. The vertically stacked p-channel poly-Si TFTs with top-gate structure on the top layer showed a high field effect mobility of 131 cm2/V-s. Therefore, the proposed structure is very suitable for future 3D-IC and nano-device application.
  • Keywords
    elemental semiconductors; silicon; thin film transistors; three-dimensional integrated circuits; Si; bottom-gate structure; field effect mobility; high-performance poly-Si TFT; n-channel poly-Si TFT; three dimensional integrated circuit; top-gate poly-Si TFT; top-gate polycrystalline silicon TFT; vertically-stacked bottom-gate polycrystalline silicon TFT; Crystallization; Electric variables; Fabrication; Films; Integrated circuits; Logic gates; Silicon; 3D-IC; Poly-Si; TFTs; bottom gate; top gate;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoelectronics Conference (INEC), 2011 IEEE 4th International
  • Conference_Location
    Tao-Yuan
  • ISSN
    2159-3523
  • Print_ISBN
    978-1-4577-0379-9
  • Electronic_ISBN
    2159-3523
  • Type

    conf

  • DOI
    10.1109/INEC.2011.5991740
  • Filename
    5991740