DocumentCode
2862566
Title
Low reverse transfer capacitance VDMOS transistor
Author
Sakai, Tatsuo ; Murakami, Naoki
Author_Institution
Appl. Electron. Lab., NTT, Tokyo, Japan
fYear
1988
fDate
11-14 April 1988
Firstpage
689
Abstract
A VDMOS (vertical double-diffused metal-oxide semiconductor) transistor structure is proposed that reduces reverse transfer capacitance. The structure features an additional p-region formed at the surface of the n-epitaxial layer, using a poly-Si gate as a mask. Its measured reverse transfer capacitance is about 50% less than that of the conventional VDMOS, and the rise time reduced 50%. measured I/sub D/-V/sub DS/, drain-source breakdown, and switching characteristics are also presented.<>
Keywords
capacitance; insulated gate field effect transistors; Si; VDMOS transistor; drain-source breakdown; mask; n-epitaxial layer; p-region; poly-Si gate; reverse transfer capacitance reduction; rise time; switching characteristics; vertical double-diffused metal-oxide semiconductor; Capacitance; Electrodes; Frequency; Laboratories; Power MOSFET; Power dissipation; Power supplies; Shape; Transistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics Specialists Conference, 1988. PESC '88 Record., 19th Annual IEEE
Conference_Location
Kyoto, Japan
Type
conf
DOI
10.1109/PESC.1988.18197
Filename
18197
Link To Document