Amorphous silicon charge storage layer of nonvolatile memory with trigate nanowires structure

Author

Chen, Hung-Bin ; Wu, Yung-Chun ; Chen, Lun-Jyun ; Chiang, Ji-Hong ; Hung, Min-Feng ; Yang, Chao-Kan ; Chang, Chun-Yen

Author_Institution

Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2011

fDate

21-24 June 2011

Firstpage

1

Lastpage

2

Abstract

This study demonstrates a trigate poly-Si nonvolatile memory (NVM) with an amorphous silicon (a-Si) charge trapping layer. The NWs SOAOS (silicon-oxide-amorphous silicon-oxide-silicon) NVM exhibits higher program/erase (P/E) efficiency than that of a conventional SONOS NVM. Moreover, SOAOS NVM shows greater endurance (>; 2.4 V after 10⁴ cycles) and longer charge retention time (>; 10⁹ s for 31% charge loss at 85°C). The result reveals that SOAOS-NVM has potential in system-on-panel and 3D stacked NVM applications.

Keywords

amorphous semiconductors; electron traps; elemental semiconductors; nanowires; random-access storage; silicon; 3D stacked NVM; NW SOAOS; SOAOS-NVM; Si; charge retention time; charge storage layer; charge trapping layer; nonvolatile memory; program/erase efficiency; silicon-oxide-amorphous silicon-oxide-silicon; system-on-panel; trigate nanowires structure; trigate poly-Si; Fabrication; Logic gates; Nonvolatile memory; SONOS devices; Silicon; Thin film transistors; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoelectronics Conference (INEC), 2011 IEEE 4th International

Conference_Location

Tao-Yuan

ISSN

2159-3523

Print_ISBN

978-1-4577-0379-9

Electronic_ISBN

2159-3523

Type

conf

DOI

10.1109/INEC.2011.5991757

Filename

5991757