Title :
Advanced FinFET process technology for 20 nm node and beyond
Author :
Masahara, M. ; Matsukawa, T. ; Endo, K. ; Liu, Y.-X. ; Mizubayashi, W. ; Migita, S. ; O´uchi, S. ; Ota, H. ; Morita, Y.
Author_Institution :
Nat. Inst. of AIST, Tsukuba, Japan
Abstract :
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.
Keywords :
MOSFET; VLSI; 3D structure; VLSI circuits; advanced FinFET process technology; double-gate FinFET; short channel effects; size 20 nm; superior SCE immunity; Annealing; Epitaxial growth; Etching; FinFETs; Logic gates; Tin; FinFET; Metal Gate; Metal S/D; NiSi2; Wet Etching;
Conference_Titel :
Nanoelectronics Conference (INEC), 2011 IEEE 4th International
Conference_Location :
Tao-Yuan
Print_ISBN :
978-1-4577-0379-9
Electronic_ISBN :
2159-3523
DOI :
10.1109/INEC.2011.5991771
