Impact of Inaccurate Design of Branch Predictors on Processors´ Power Consumption

In CMPs (Chip Multi-Processors) with thousand of processors, the issue of power dissipation has emerged out as a matter of serious concern. Out of the several factors responsible for processor power dissipation, the branch prediction unit of a modern processor itself contributes to almost 10% of the overall power dissipation. It points to the fact that the functioning of predictors is to be more accurate as well as power efficient. In this work, we analyze the impact of inaccurate/faulty design on the branch predictors´ power dissipation while realizing speculative execution. This issue has been addressed through introduction of probable faults, commonly arise out of the design inaccuracies, in a predictor that lead to mis-speculation. The evaluation of fault effect (design inaccuracy) is done by estimating the additional power consumed by a pipelined processor. The detail analysis reveals that the design inaccuracy/fault in a predictor can cause a huge power loss, even up to 95%.