Learning based address mapping for improving the performance of memory subsystems

Interleaved address mapping has been effectively used to improve the performance of a parallely accessible memory subsystem. We propose a generalization of such mappings and study them in the framework of application specific MPSoCs. In this generalization, a section of the address bits is used to map each address to a memory bank and a row within that bank, using a look-up table(LUT). We model the problem of address mapping optimization as a Markov decision process (MDP). To solve the MDP, we propose a reinforcement learning based algorithm which learns an optimized mapping within the generalized class, for a specific application mapped to an MPSoC system. Through cycle-accurate simulations on a simulation framework specifically developed for such a study, we demonstrate that a system using an address mapping generated in this manner exhibits substantially higher performance when compared to the same system using interleaved address mappings. These results indicate that application and architecture visibility can be leveraged to obtain better mappings than generic interleaved solutions, and that an automated reinforcement learning approach can identify such mappings using only the run-time behaviour of the system.