A low noise multi-PFD PLL with timing shift circuit

A low noise multi-PFD PLL with timing shift circuit is presented. It utilize parallel circuit configuration to improve SNR of the circuit. To enhance the effect of reducing noise, timing shift circuit is proposed. The proposed architecture includes a delay circuit of VCO signal and a mechanism to adjust the phase of reference signals automatically. The proposed PLL is demonstrated using a custom 0.18µm SiGe-BiCMOS integrated circuit. The experimental results show the effectiveness of noise-reduction by timing shift mode, and in-band phase noise of −114.2dBc/Hz is achieved at 15GHz. The normalized PLL phase noise floor of −237.7dBc/Hz is the lowest value among the reported PLL-ICs.