Title :
LSI chip design for testability
Author :
Dasgupta, S. ; Eichelberger, E. ; Williams, Tyson
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
The design of LSI chips for testability using shift register latches as the basic storage units in level sensitive scan application will be discussed. Examples of circuits using this technique will also be offered.
Keywords :
Automatic testing; Chip scale packaging; Circuit testing; Clocks; Fault detection; Feedback loop; Large scale integration; Latches; Logic testing; Shift registers;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1978.1155765
