Title :
A 75.5-to-120.5-GHz, high-gain CMOS low-noise amplifier
Author :
Lu, De-Ren ; Hsu, Yu-Chung ; Kao, Jui-Chih ; Kuo, Jhe-Jia ; Niu, Dow-Chih ; Lin, Kun-You
Author_Institution :
Department of Electrical Engineering and Graduate Institute of Communication Engineering, National Taiwan University, Taipei 10617, Taiwan
Abstract :
In this paper, a high-gain and wideband low-noise amplifier using 65-nm CMOS process is proposed. A four-stage cascode configuration is adopted to achieve the high gain and wideband performance. With 24-mA dc current and 2-V supply voltage, the LNA not only provides gain higher than 20 dB from 75.5 GHz to 120.5 GHz, but also has a measured noise figure between 6 and 8.3 dB from 87 to 100 GHz. The output 1-dB compression power (OP1dB) is −3 dBm at 110 GHz, and the chip size is 0.55 × 0.45 mm2.
Keywords :
CMOS integrated circuits; Gain; Noise figure; Semiconductor device measurement; Transmission line measurements; Wideband; CMOS; MMIC; W-band; low noise amplifier;
Conference_Titel :
Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International
Conference_Location :
Montreal, QC, Canada
Print_ISBN :
978-1-4673-1085-7
Electronic_ISBN :
0149-645X
DOI :
10.1109/MWSYM.2012.6259481
