DocumentCode
2864814
Title
A high-speed low-power 4096 × 1-bit bipolar RAM
Author
Hotta, Abhilash ; Kato, Yu ; Yamaguchi, Kazuhiro ; Honma, Naoki ; Inadachi, M.
Author_Institution
Hitachi, Ltd., Tokyo, Japan
Volume
XXI
fYear
1978
fDate
15-17 Feb. 1978
Firstpage
98
Lastpage
99
Abstract
Circuit techniques to reduce power consumption of a 25ns, TTL, 4K-bit static bipolar RAM to as low as 350 mW will be discussed.
Keywords
Decoding; Delay; Driver circuits; Electric variables; Metallization; Paper technology; Power dissipation; Read-write memory; Schottky diodes; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1978.1155784
Filename
1155784
Link To Document