Title :
FET logic configuration
Author :
Blaser, E. ; Conrad, D.
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
Abstract :
A FET logic configuration that uses both enhancement-mode and depletion-mode devices in a single-input, multiple-output logic circuit, will be covered, citing improvement of power-delay product by a factor of four.
Keywords :
Capacitance; Circuit noise; Delay; FET circuits; Logic circuits; Logic devices; Noise figure; Noise level; Noise reduction; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1978.1155813
