• DocumentCode
    2865307
  • Title

    FET logic configuration

  • Author

    Blaser, E. ; Conrad, D.

  • Author_Institution
    IBM Corp., Hopewell Junction, NY, USA
  • Volume
    XXI
  • fYear
    1978
  • fDate
    15-17 Feb. 1978
  • Firstpage
    14
  • Lastpage
    15
  • Abstract
    A FET logic configuration that uses both enhancement-mode and depletion-mode devices in a single-input, multiple-output logic circuit, will be covered, citing improvement of power-delay product by a factor of four.
  • Keywords
    Capacitance; Circuit noise; Delay; FET circuits; Logic circuits; Logic devices; Noise figure; Noise level; Noise reduction; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1978.1155813
  • Filename
    1155813
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2865307