Title :
A 100ns 150mW 64Kbit ROM
Author :
Wilson, D. ; Schroeder, P.
Author_Institution :
Mostek, Inc., Carrollton, TX, USA
Abstract :
A sub 100ns 64K ROM using standard N-channel silicon-gate technology will be discussed. The ROM organized as 8K words by 8bits per word operates from a single 5V supply and has a typical access time and power of 80ns and 150mW.
Keywords :
Clocks; Data buses; Decoding; Differential amplifiers; Implants; Latches; Read only memory; Silicon; Threshold voltage; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1978.1155829
