Title :
Design of a guaranteed throughput router for on-chip networks
Author :
Sathe, Sumant ; Wiklund, Daniel ; Liu, Dake
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
The complexity of system-on-chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. On-chip networks (OCNs) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router We present a prototype design of a 5-input, 5-output, scalable guaranteed throughput (GT) router The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN. The router supports wormhole routing, and is characterized by an area of 0.1 mm2 in 0.18 micron CMOS technology.
Keywords :
CMOS integrated circuits; circuit CAD; circuit complexity; integrated circuit design; integrated circuit interconnections; multiprocessor interconnection networks; network routing; system-on-chip; 0.18 micron; CMOS technology; OCN router; SoC; basic OCN building block; billion transistor chips; bus-based interconnects; communication requirements; guaranteed throughput router design; on-chip networks; parameterizable reusable hardware blocks; prototype design; system-on-chip design complexity; wormhole routing; Clocks; Delay; Hardware; Network-on-a-chip; Repeaters; Routing; System recovery; Telecommunication traffic; Throughput; Wires;
Conference_Titel :
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN :
0-7803-8558-6
DOI :
10.1109/ISSOC.2004.1411137
