Title :
A 920 gate masterslice
Author :
Nakano, T. ; Tomisawa, O. ; Anami, K. ; Nakaya, M. ; Ohmori, M. ; Ohkura, I.
Author_Institution :
Mitsubishi Electronic Corp., Hyogo, Japan
Abstract :
An MOS masterslice chip with up to 920 gates, 3W dissipation and 3ns/gate propagation delay time for random logic LSIs will be reported.
Keywords :
Capacitance; Delay effects; Large scale integration; Pins; Power supplies; Propagation delay; Registers; Ring oscillators;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1978.1155845
