A low-power I-cache design with tag-comparison reuse

Author

Inoue, Koji ; Tanaka, Hidekazu ; Moshnyaga, Vasily G. ; Murakami, Kazualu

Author_Institution

Dept. of Elec. Eng. & Comput. Sci., Fukuoka Univ., Japan

fYear

2004

fDate

16-18 Nov. 2004

Firstpage

61

Lastpage

67

Abstract

This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to detect and eliminate unnecessary memory-array activations. We have performed cycle accurate simulations, and have designed an SRAM core based on a 0.18 μm CMOS technology. As a result, it has been observed that the HBTC approach can achieve 60% of energy reduction, with only 0.3% performance degradation, compared to a conventional cache. Furthermore, we have also evaluated the potential of the HBTC cache by combining with other low-energy techniques.

Keywords

CMOS memory circuits; SRAM chips; cache storage; circuit simulation; integrated circuit design; low-power electronics; system-on-chip; 0.18 micron; CMOS SRAM core design; HBTC cache; cycle accurate simulations; energy reduction; history-based tag-comparison cache; low-energy I-cache architecture; low-energy techniques; low-power I-cache design; performance degradation; tag-comparison reuse; unnecessary memory-array activations; CMOS technology; Computer architecture; Computer science; Degradation; Delay; Energy consumption; Frequency; Informatics; Pins; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2004. Proceedings. 2004 International Symposium on

Print_ISBN

0-7803-8558-6

Type

conf

DOI

10.1109/ISSOC.2004.1411147

Filename

1411147