Title :
A 64Kbit CCD memory
Author :
Varshney, R. ; Venkateswaran, K.
Author_Institution :
Fairchild Camera and Instrument Corp., Palo Alto, CA, USA
Abstract :
This paper will cover the design and performance of a 64Kbit buried channel CCD memory, operating over 1-5MHz, and using 8-phase ripple clocks within an interlaced series-parallel-series structure. Chip size is 4.4 × 5.8mm2, packaged in a standard 16-pin 300-mil wide assembly.
Keywords :
Charge coupled devices; Charge transfer; Clocks; Delay; Latches; Logic arrays; Packaging; Shift registers; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1978.1155860
