DocumentCode
2866222
Title
Evaluation of the yield impact of epitaxial defects on advanced semiconductor technologies
Author
Williams, Randy ; Jacques, Robert ; Akbulut, Mustafa ; Chen, Wayne
Author_Institution
Intel Corp., Rio Rancho, NM, USA
fYear
2000
fDate
2000
Firstpage
1
Lastpage
7
Abstract
Epitaxial defects (e.g., stacking faults, epi-spikes, mounds, hillocks, and pits) can often impact product yields, depending upon the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. However, the overall yield impact from epitaxial defects has been difficult to assess since the defect sensitivity, capture rates, and classification for these defects has often been poor on product wafers. In a collaborative study between Intel Corporation and KLA-Tencor Corporation, the SP1TBI defect inspection system was used to inspect and classify epitaxial wafers for an advanced semiconductor manufacturing process. After completion of the semiconductor processing, the defect kill rates and the yield impact were evaluated using bitmapping analysis. The project results demonstrate that the enhanced defect sensitivity and better capture rate of the SP1TBI inspection system can provide a significant improvement in the defect inspection capabilities currently being utilized for epitaxial wafers. The SP1TBI inspection system was also able to successfully classify particles and epitaxial defects using real-time defect classification (RTDC), with greater than 99 percent accuracy. The epitaxial defect levels and the corresponding product yield impact were observed to vary significantly between major silicon wafer suppliers. Consequently, these results can be useful in the development of tighter defect specifications for epitaxial wafers to minimize the resulting yield loss from epitaxial defects
Keywords
crystal defects; inspection; integrated circuit testing; integrated circuit yield; semiconductor epitaxial layers; stacking faults; SP1 defect inspection system; advanced semiconductor manufacturing process; bitmapping analysis; capture rates; defect kill rates; defect sensitivity; defect specifications; epi-spikes; epitaxial defects; hillocks; mounds; pits; product yields; real-time defect classification; stacking faults; yield impact; yield sensitivity; CMOS technology; Collaboration; Crystallization; Electronics industry; Inspection; Manufacturing processes; Real time systems; Semiconductor films; Silicon; Stacking;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI
Conference_Location
Boston, MA
ISSN
1078-8743
Print_ISBN
0-7803-5921-6
Type
conf
DOI
10.1109/ASMC.2000.902550
Filename
902550
Link To Document