Title :
A synthesizable RTL design of asynchronous FIFO
Author :
Wang, Xin ; Ahonen, Tapani ; Nurmi, Jari
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Abstract :
An asynchronous FIFO which avoids data movement in a micropipeline FIFO is presented and it has been implemented as a gate-level netlist. The presented asynchronous FIFO model is constructed by commonly used hardware-description language and synthesized using the conventional EDA tools and methods for synchronous design. The purpose of this work is to construct a reusable asynchronous FIFO design which suits the commonly used synchronous design tools and flow.
Keywords :
asynchronous circuits; hardware description languages; integrated circuit design; logic CAD; pipeline processing; system-on-chip; EDA methods; EDA tools; SoC; asynchronous FIFO model; data movement; gate-level netlist; hardware-description language; micropipeline FIFO; reusable asynchronous FIFO design; synchronous design; synthesizable RTL design; system-on-chip design; Asynchronous communication; Clocks; Counting circuits; Delay; Design methodology; Electronic design automation and methodology; Hardware design languages; Logic; Signal processing; System-on-a-chip;
Conference_Titel :
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN :
0-7803-8558-6
DOI :
10.1109/ISSOC.2004.1411164
