A technology development SRAM approach with DFM considerations

Author

Craig, M. ; Deshazo, D. ; Prior, S. ; Tranchina, B. ; Erhart, M. ; Mahant-Shetti, S.S. ; Taylor, R. ; Xing, Y. ; Quek, E. ; Chok, K.L. ; Kamat, N. ; Redford, M.

Author_Institution

Testchip Technol. Inc., Dallas, TX, USA

fYear

2000

fDate

2000

Firstpage

89

Lastpage

91

Abstract

A technology development SRAM (TDSRAM^TM) has been highly effective in rapid process technology development, debug, and yield ramp on an advanced CMOS, 0.18 μm foundry process technology. TDSRAM is seen to accelerate FEOL and BEOL process debug using technology-oriented design and test approaches while minimizing inherent functional risks associated with IP-like designs at early stages of new technology development programs. Smart array design approaches have proven effective in directing immediate and focused failure analysis activities for rapid identification of root cause failure mechanisms

Keywords

CMOS memory circuits; SRAM chips; design for manufacture; failure analysis; integrated circuit design; integrated circuit yield; 0.18 micron; BEOL; CMOS; DFM considerations; FEOL; TDSRAM; failure mechanisms; foundry process technology; rapid process technology development; smart array design; technology development SRAM; technology-oriented design; yield ramp; CMOS technology; Circuit testing; Contacts; Delay; Design for manufacture; Failure analysis; Job shop scheduling; Manufacturing processes; Random access memory; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5921-6

Type

conf

DOI

10.1109/ASMC.2000.902564

Filename

902564