Defect localization using physical design and electrical test information

Author

Stanojevic, Zoran ; Balachandran, Hari ; Walker, D.M.H. ; Lakhani, Fred ; Jandhyala, Sri

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

2000

fDate

2000

Firstpage

108

Lastpage

115

Abstract

In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to correctly identify the defect location and layer in all 9 of the chips that had bridging faults injected via FIB. Preliminary failure analysis results on production defects are promising

Keywords

automatic test pattern generation; failure analysis; fault diagnosis; focused ion beam technology; integrated circuit design; integrated circuit testing; logic testing; production testing; ATPG tool; CAFDM; FIB; bridging faults; computer-aided fault to defect mapping; defect localization; electrical test information; failure knowledge; physical design; production defects; random logic; Automatic test pattern generation; Circuit faults; Circuit testing; Failure analysis; Fault diagnosis; Inspection; Instruments; Logic testing; Scanning electron microscopy; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5921-6

Type

conf

DOI

10.1109/ASMC.2000.902568

Filename

902568