Title :
Comparative analysis of serial vs parallel links in NoC
Author :
Morgenshtein, Arkadiy ; Cidon, Israel ; Kolodny, Avinoam ; Ginosar, Ran
Author_Institution :
Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
Abstract :
An analytical model is employed to characterize and compare serial and parallel communication techniques in NoC interconnects. Simulations that are based on 130 nm and 70 nm technology parameters reveal up to ×5.5 and ×17 reduction in power and area of serial vs. 32-bit multi-layer parallel links, respectively. Lower power is dissipated by a single-layer parallel link but it occupies a larger area. We conclude that long on-chip interconnects could benefit from serial links.
Keywords :
integrated circuit interconnections; integrated circuit modelling; multiprocessor interconnection networks; system buses; system-on-chip; 130 nm; 32 bit; 70 nm; NoC interconnect communication techniques; NoC multilayer parallel links; NoC serial links; long on-chip interconnects; packet-switched networks on-chip; single-layer parallel link; Analytical models; Clocks; Crosstalk; Delay; Integrated circuit interconnections; Network-on-a-chip; Repeaters; Switches; Throughput; Wire;
Conference_Titel :
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN :
0-7803-8558-6
DOI :
10.1109/ISSOC.2004.1411181
