• DocumentCode
    2866826
  • Title

    Self Checking in Current Floating-Point Units

  • Author

    Lipetz, Daniel ; Schwarz, Eric

  • Author_Institution
    Syst. & Technol. Group, IBM Corp, Poughkeepsie, NY, USA
  • fYear
    2011
  • fDate
    25-27 July 2011
  • Firstpage
    73
  • Lastpage
    76
  • Abstract
    High performance microprocessors are protected against transient and early end of life failures using a variety of error detection and fault isolation technologies. Execution units can be protected with duplication, parity prediction, or residue checking. Residue checking has an advantage due to its small size. A modulus is selected based on the radix of the numbers being checked. In a decimal floating-point unit there are two types of numbers in different bases. There are base 10 decimal numbers and base 2 integers being used. A residue checking system that makes it easy to check both base 2 and 10 numbers is discussed. Current state of the art designs that are currently in use are described as well as a novel hybrid moduli 9 and 3 residue system. The checking systems for the decimal and binary floating-point units of some recent IBM microprocessors including the Power6, Power7, z10, and z196 microprocessors are detailed.
  • Keywords
    error detection; floating point arithmetic; microprocessor chips; IBM microprocessor; decimal floating point unit; error detection; fault isolation; high performance microprocessor; residue checking system; self checking; Adders; CMOS integrated circuits; Logic gates; Microprocessors; Multiplexing; Radiation detectors; Transient analysis; error detection; fault isolation; floating-point unit; microprocessor design; residue checking; self checking;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 2011 20th IEEE Symposium on
  • Conference_Location
    Tubingen
  • ISSN
    1063-6889
  • Print_ISBN
    978-1-4244-9457-6
  • Type

    conf

  • DOI
    10.1109/ARITH.2011.18
  • Filename
    5992110