Clock generation and distribution in high-performance processors

This paper is an overview of clock generation and distribution techniques, with emphasis on high-performance microprocessor designs. We describe practical techniques to reduce clock skew and jitter, with examples from several industry leaders. As power consumption is a limiting factor for all modern designs, low-power clock distribution techniques and flip-flop implementations are reviewed. Several clock-related design-for-test and debug techniques are described, with practical implementation examples.