An integrated hardmask/poly RIE process for sub-0.25 um gate etch

Summary form only given. We have evaluated an integrated Polysilicon etch process for sub-0.25 um logic products by combining the dielectric hardmask open and poly etches into a one-pass reactive ion etch (RIE) process using a low-pressure TCP Poly etch tool. With this process we also investigated a CD line-width reduction etch (Trim) in which the Polysilicon line-width was significantly reduced to increase device speed. One advantage to be expected from this Trim etch would be an improved line-width control. The low-pressure environment ensures less lateral attack of the resist from the etch species during the mask open and allows better control of gate line-width, across-wafer and across-chip