Title :
Circuit optimization of the taper isolated dynamic gain RAM cell for VLSI memories
Author :
Chatterjee, Parag ; Taylor, Gareth ; Malwah, M.
Author_Institution :
Texas Instruments, Inc., Dallas, TX, USA
Abstract :
A one transistor only, ROM like dynamic RAM cell, whose operation depends on the modulation of the threshold of a buried channel device by a hole packet, derived from the channel stop region will be covered. Tapered oxide between the field and gate oxide is used to form a potential barrier for holes.
Keywords :
Artificial intelligence; Circuit optimization; Clocks; Electrodes; Geometry; Laboratories; Random access memory; Silicon; Threshold voltage; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1979.1155921
